This invention relates to a double balance type switching circuit. Various forms of double balance type switching circuits are already known. FIG. 1 illustrates a prior art double balance type switching circuit. A differential amplifier 4 included in this switching circuit is formed of npn transistors TR1 and TR2 whose emitters are connected together through resistors R1 and R2 and whose bases are respectively connected to signal input terminals 1 and 2; and a current source 3 connected between the junction of the resistors R1 and R2 and the ground. The collector of the transistor TR1 is connected to the common emitter of npn transistors TR3 and TR4 constituting another differential amplifier 5. The collector of the transistor TR2 is connected to the common emitter of npn transistors TR5 and TR6 constituting a third differential amplifier 6. The bases of the transistors TR3 and TR6 are connected to a switching control terminal 7. The bases of the transistors TR4 and TR5 are connected to another switching control terminal 8. The collectors of the transistors TR3 and TR5 are directly connected to a power supply terminal V.sub.cc. The collectors of the transistors TR4 and TR6 are connected to the power supply terminal V.sub.cc through a resistor R3, and are also connected to the base of an npn transistor TR7 whose collector is connected to the power supply terminal V.sub.cc and whose emitter is grounded through a current source 9. The output terminal V.sub.o of this switching circuit is connected to the emitter of the transistor TR7.
There will now be described the operation of the prior art double balance type switching circuit of FIG. 1 by reference to the signal waveforms of FIGS. 2 to 5. The solid and broken lines of FIG. 2 respectively indicate the waveforms of switching control signals supplied to the switching control terminals 7 and 8. FIG. 3 shows the waveform of a signal supplied between the signal input terminals 1 and 2. When switching control voltage impressed on the switching control terminal 7 is higher than that supplied to the switching control terminal 8, namely, when the control voltage represented by the solid line of FIG. 2 is higher than the control voltage denoted by the broken line of FIG. 2, then the transistors TR3 and TR6 are rendered conductive, and the transistors TR4 and TR5 become nonconductive. Accordingly, the collector current of the transistor TR2 flows through the current path of the transistor TR6, now rendered conductive, and resistor R3. Conversely, when the switching control voltage supplied to the switching control terminal 7 is lower than that impressed on the switching control terminal 8, then the transistors TR4 and TR5 are rendered conductive, and the transistors TR3 and TR6 are rendered nonconductive. As the result, the collector current of the transistor TR1 runs through the current path of the transistor TR4 now rendered conductive and resistor R3. It should be noted in this case that current signals of the opposite phases corresponding to alternating voltage V.sub.s impressed across the signal input terminals 1 and 2 run through the collectors of the transistors TR1 and TR2 jointly constituting the differential amplifier 4. Therefore, current flowing through the resistor R3 when the switching control voltage supplied to the switching control terminal 7 is higher than that impressed on the switching control terminal 8 has the opposite phase of the current running through the resistor R3 where the switching control voltage supplied to the switching control terminal 7 is lower than that impressed on the switching control terminal 8. The base of the transistor TR7 is supplied with voltage corresponding to the current conducted through the resistor R3. Therefore, the emitter voltage of the transistor TR7, namely, an output voltage from the output terminal V.sub.o has the same phase as the input voltage V.sub.s, where, as shown in FIG. 4, the switching control voltage supplied to the switching control terminal 7 is higher than that impressed on the switching control terminal 8, and has the opposite phase to the input voltage V.sub.s, when the switching control voltage supplied to the switching control terminal 7 is lower than that impressed on the switching control terminal 8.
With the prior art double balance type switching circuit of FIG. 1 arranged as described above, proper conversion of the switching control voltage makes it possible selectively to produce an output signal having a phase the same as or opposite to that of an input signal.
However, the prior art double balance type switching circuit of FIG. 1 has the drawback that a parasitic capacitor appears in the collectors of the transistors TR1 and TR2 (a capacity prevailing between the collectors and the substrate in the IC switching circuit). A sharp drop in the switching control voltage impressed on the switching control terminal 7 (FIG. 2) leads to a sudden change in the emitter potentials of the transistors TR3, TR4, TR5 and TR6 and in consequence the collector potentials of the transistors TR1 and TR2. Such rapid variation in the collector voltage of the transistors TR1 and TR2 causes extra current to charge and discharge the above-mentioned parasitic capacitor of the transistors TR1 and TR2. The extra current is superposed on the collector current of the transistors TR1 and TR2, causing a spike voltage (FIG. 5) to occur in the resistor R3. FIG. 5 illustrates a spike voltage appearing at the output terminal V.sub.o, when the signal input terminals 1 and 2 are connected together. The spike voltage grows higher, accordingly as sharper changes appear in the level of the switching control voltage impressed on the switching control terminals 7 and 8, harmfully effecting a circuit connected in the following stage of the double balance type switching circuit.